 

// SystemVerilog file 
 
module SCAL (
    // Interface to the ISAX Module
    
    input  [32 -1 : 0] WrRD_ISAX1_3_i,// ISAX
    input   WrRD_validReq_ISAX1_3_i,// ISAX
    output  [32 -1 : 0] RdInstr_2_o,// ISAX
    output  [32 -1 : 0] RdRS1_2_o,// ISAX
    output  [32 -1 : 0] RdRS2_2_o,// ISAX
    output   RdIValid_ISAX1_2_o,// ISAX
    
    
    // Interface to the Core
    
    output reg [32 -1 : 0] WrRD_3_o,// ISAX
    output reg  WrRD_validReq_3_o,// ISAX
    input  [32 -1 : 0] RdInstr_2_i,// ISAX
    input  [32 -1 : 0] RdRS1_2_i,// ISAX
    input  [32 -1 : 0] RdRS2_2_i,// ISAX
    input   RdFlush_2_i,// ISAX
    input   RdFlush_3_i,// ISAX
    input  [32 -1 : 0] RdInstr_3_i,// ISAX
    
    input clk_i,
    input rst_i
    
    
);
// Declare local signals
wire  RdIValid_ISAX1_2_s;
wire  RdIValid_ISAX1_3_s;
wire  RdFlush_3_s;
wire  RdFlush_2_s;


// Logic
assign RdInstr_2_o = RdInstr_2_i;
assign RdRS1_2_o = RdRS1_2_i;
assign RdRS2_2_o = RdRS2_2_i;
assign RdIValid_ISAX1_2_o = RdIValid_ISAX1_2_s;
assign RdIValid_ISAX1_2_s = (  ( RdInstr_2_i [ 14 ]  ==  1'b0 )  &&  ( RdInstr_2_i [ 13 ]  ==  1'b1 )  &&  ( RdInstr_2_i [ 12 ]  ==  1'b1 )  &&  ( RdInstr_2_i [ 6 ]  ==  1'b0 )  &&  ( RdInstr_2_i [ 5 ]  ==  1'b0 )  &&  ( RdInstr_2_i [ 4 ]  ==  1'b0 )  &&  ( RdInstr_2_i [ 3 ]  ==  1'b1 )  &&  ( RdInstr_2_i [ 2 ]  ==  1'b0 )  &&  ( RdInstr_2_i [ 1 ]  ==  1'b1 )  &&  ( RdInstr_2_i [ 0 ]  ==  1'b1 )  ) && !RdFlush_2_s;
assign RdIValid_ISAX1_3_s = (  ( RdInstr_3_i [ 14 ]  ==  1'b0 )  &&  ( RdInstr_3_i [ 13 ]  ==  1'b1 )  &&  ( RdInstr_3_i [ 12 ]  ==  1'b1 )  &&  ( RdInstr_3_i [ 6 ]  ==  1'b0 )  &&  ( RdInstr_3_i [ 5 ]  ==  1'b0 )  &&  ( RdInstr_3_i [ 4 ]  ==  1'b0 )  &&  ( RdInstr_3_i [ 3 ]  ==  1'b1 )  &&  ( RdInstr_3_i [ 2 ]  ==  1'b0 )  &&  ( RdInstr_3_i [ 1 ]  ==  1'b1 )  &&  ( RdInstr_3_i [ 0 ]  ==  1'b1 )  ) && !RdFlush_3_s;
always @(*)  WrRD_3_o = WrRD_ISAX1_3_i;
always @(*) begin 
    case(1'b1)
        RdIValid_ISAX1_3_s : WrRD_validReq_3_o = WrRD_validReq_ISAX1_3_i;
        default : WrRD_validReq_3_o = ~1;
    endcase
end
assign RdFlush_3_o = RdFlush_3_s;
assign RdFlush_3_s = RdFlush_3_i;
assign RdFlush_2_o = RdFlush_2_s;
assign RdFlush_2_s = RdFlush_2_i;


endmodule





